1. Field of the Invention
This invention relates to processors. More specifically, this invention relates to processors that execute CISC-type instructions on a RISC core.
2. Description of the Related Art
Advanced microprocessors, such as P6-class x86 processors, are defined by a common set of features. These features include a superscalar architecture and performance, decoding of multiple x86 instructions per cycle and conversion of the multiple x86 instructions into RISC-like operations. The RISC-like operations are executed out-of-order in a RISC-type core that is decoupled from decoding. These advanced microprocessors support large instruction windows for reordering instructions and for reordering memory references.
Although RISC processors are considered by many to be architecturally superior to CISC processors in most applications, CISC processors continue to dominate the computer market due to the large base of legacy software that is installed in computers.
Computer system users and designers would be greatly benefited by a processor that optimizes processor performance and avoids performance degradation that invariably results from a requirement to support legacy software. Several CISC processor designs have been developed that attempt to improve performance while supporting old software. These designs typically utilize a RISC processor inside the shell of a CISC processor and include a translating or decoding circuit to read CISC-type instructions, translate the CISC-type instructions into RISC instructions, and deliver resulting RISC codes to a RISC core for execution. Performance improvements have resulted from these hybrid CISC-RISC processors. Unfortunately much of the performance that could be attained by the RISC processing cores is restrained by the CISC interface.
What is needed is a processor and operating technique for selectively executing either CISC-type instructions or RISC-type instructions while substantially avoiding performance degradation that results from translation of CISC-type instructions to RISC operation codes.